Claudia Feregrino-Uribe
Claudia Feregrino-Uribe
Professor of Computer Science, National Institute for Astrophysics, Optics and Electronics
Verified email at inaoep.mx
Title
Cited by
Cited by
Year
An FPGA-based parallel sorting architecture for the Burrows Wheeler transform
J Martinez, R Cumplido, C Feregrino
Reconfigurable Computing and FPGAs, 2005. ReConFig 2005. International …, 2005
642005
Bit-serial and digit-serial GF (2m) Montgomery multipliers using linear feedback shift registers
M Morales-Sandoval, C Feregrino-Uribe, P Kitsos
IET Computers & Digital Techniques 5 (2), 86-94, 2011
452011
FPGA hardware architecture of the steganographic context technique
E Gomez-Hernandez, C Feregrino-Uribe, R Cumplido
18th International Conference on Electronics, Communications and Computers …, 2008
382008
A versatile linear insertion sorter based on an FIFO scheme
R Perez-Andrade, R Cumplido, C Feregrino-Uribe, FM Del Campo
Microelectronics Journal 40 (12), 1705-1713, 2009
372009
FPGA-based implementation alternatives for the inner loop of the Secure Hash Algorithm SHA-256
I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval
Microprocessors and Microsystems 37 (6-7), 750-757, 2013
312013
An area/performance trade-off analysis of a GF (2m) multiplier architecture for elliptic curve cryptography
M Morales-Sandoval, C Feregrino-Uribe, R Cumplido, I Algredo-Badillo
Computers & Electrical Engineering 35 (1), 54-58, 2009
302009
A compact FPGA-based processor for the Secure Hash Algorithm SHA-256
R García, I Algredo-Badillo, M Morales-Sandoval, C Feregrino-Uribe, ...
Computers & Electrical Engineering 40 (1), 194-202, 2014
272014
On the hardware design of an elliptic curve cryptosystem
M Morales-Sandoval, C Feregrino-Uribe
Proceedings of the Fifth Mexican International Conference in Computer …, 2004
262004
A hardware architecture for elliptic curve cryptography and lossless data compression
MM Sandoval, C Feregrino-Uribe
15th International Conference on Electronics, Communications and Computers …, 2005
232005
A reconfigurable GF(2M) elliptic curve cryptographic coprocessor
M Morales-Sandoval, C Feregrino-Uribe, R Cumplido, I Algredo-Badillo
2011 VII Southern Conference on Programmable Logic (SPL), 209-214, 2011
222011
FPGA implementation and performance evaluation of AES-CCM cores for wireless networks
I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval
2008 International Conference on Reconfigurable Computing and FPGAs, 421-426, 2008
222008
Adaptive Steganography based on textures
DR Herrera-Moro, R Rodríguez-Colín, C Feregrino-Uribe
17th International Conference on Electronics, Communications and Computers …, 2007
222007
High payload data-hiding in audio signals based on a modified OFDM approach
JJ Garcia-Hernandez, R Parra-Michel, C Feregrino-Uribe, R Cumplido
Expert Systems with Applications 40 (8), 3055-3064, 2013
202013
Efficient hardware architecture for the AES-CCM protocol of the IEEE 802.11 i standard
I Algredo-Badillo, C Feregrino-Uribe, R Cumplido, M Morales-Sandoval
Computers & Electrical Engineering 36 (3), 565-577, 2010
202010
Area/performance trade-off analysis of an FPGA digit-serial GF (2m) Montgomery multiplier based on LFSR
M Morales-Sandoval, C Feregrino-Uribe, P Kitsos, R Cumplido
Computers & Electrical Engineering 39 (2), 542-549, 2013
182013
Watermarking using similarities based on fractal codification
PA Hernandez-Avalos, C Feregrino-Uribe, R Cumplido
Digital Signal Processing 22 (2), 324-336, 2012
162012
Design and implementation of an FPGA-Based 1.452-gbps non-pipelined AES architecture
I Algredo-Badillo, C Feregrino-Uribe, R Cumplido
International Conference on Computational Science and Its Applications, 456-465, 2006
162006
X-MatchPRO: A ProASIC-based 200 Mbytes/s full-duplex lossless data compressor
JL Nunez, C Feregrino, S Jones, S Bateman
International Conference on Field Programmable Logic and Applications, 613-617, 2001
162001
A versatile hardware architecture for a constant false alarm rate processor based on a linear insertion sorter
R Perez-Andrade, R Cumplido, C Feregrino-Uribe, FM Del Campo
Digital Signal Processing 20 (6), 1733-1747, 2010
152010
Towards the construction of a benchmark for video watermarking systems: Temporal desynchronization attacks
PA Hernandez-Avalos, C Feregrino-Uribe, R Cumplido, ...
2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 628-631, 2010
152010
The system can't perform the operation now. Try again later.
Articles 1–20