| Three-dimensional integrated circuits AW Topol, DC La Tulipe, L Shi, DJ Frank, K Bernstein, SE Steen, A Kumar, ... IBM Journal of Research and Development 50 (4.5), 491-506, 2006 | 736 | 2006 |
| Silicon device scaling to the sub-10-nm regime M Ieong, B Doris, J Kedzierski, K Rim, M Yang Science 306 (5704), 2057-2060, 2004 | 550 | 2004 |
| Characteristics and device design of sub-100 nm strained Si N-and PMOSFETs K Rim, J Chu, H Chen, KA Jenkins, T Kanarsky, K Lee, A Mocuta, H Zhu, ... 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No …, 2002 | 372 | 2002 |
| Extension and source/drain design for high-performance FinFET devices J Kedzierski, M Ieong, E Nowak, TS Kanarsky, Y Zhang, R Roy, D Boyd, ... IEEE Transactions on Electron Devices 50 (4), 952-958, 2003 | 333 | 2003 |
| Strained Si NMOSFETs for high performance CMOS technology K Rim, S Koester, M Hargrove, J Chu, PM Mooney, J Ott, T Kanarsky, ... 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No …, 2001 | 305 | 2001 |
| FinFET design considerations based on 3-D simulation and analytical modeling G Pei, J Kedzierski, P Oldiges, M Ieong, ECC Kan IEEE Transactions on Electron Devices 49 (8), 1411-1419, 2002 | 294 | 2002 |
| High performance CMOS fabricated on hybrid substrate with different crystal orientations M Yang, M Ieong, L Shi, K Chan, V Chan, A Chou, E Gusev, K Jenkins, ... IEEE International Electron Devices Meeting 2003, 18.7. 1-18.7. 4, 2003 | 286 | 2003 |
| High-performance symmetric-gate and CMOS-compatible V/sub t/asymmetric-gate FinFET devices J Kedzierski, DM Fried, EJ Nowak, T Kanarsky, JH Rankin, H Hanafi, ... International Electron Devices Meeting. Technical Digest (Cat. No. 01CH37224 …, 2001 | 262 | 2001 |
| Metal-gate FinFET and fully-depleted SOI devices using total gate silicidation J Kedzierski, E Nowak, T Kanarsky, Y Zhang, D Boyd, R Carruthers, ... Digest. International Electron Devices Meeting,, 247-250, 2002 | 253 | 2002 |
| Extreme scaling with ultra-thin Si channel MOSFETs B Doris, M Ieong, T Kanarsky, Y Zhang, RA Roy, O Dokumaci, Z Ren, ... Digest. International Electron Devices Meeting,, 267-270, 2002 | 246 | 2002 |
| Enabling SOI-based assembly technology for three-dimensional (3D) integrated circuits (ICs) AW Topol, DC La Tulipe, L Shi, SM Alam, DJ Frank, SE Steen, J Vichiconti, ... IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest …, 2005 | 214 | 2005 |
| Monte Carlo modeling of threshold variation due to dopant fluctuations DJ Frank, Y Taur, M Ieong, HSP Wong 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No. 99CH36326 …, 1999 | 214 | 1999 |
| Germanium channel MOSFETs: Opportunities and challenges H Shang, MM Frank, EP Gusev, JO Chu, SW Bedell, KW Guarini, M Ieong IBM Journal of Research and Development 50 (4.5), 377-386, 2006 | 208 | 2006 |
| Self-aligned n-channel germanium MOSFETs with a thin Ge oxynitride gate dielectric and tungsten gate H Shang, KL Lee, P Kozlowski, C D'emic, I Babich, E Sikorski, M Ieong, ... IEEE Electron Device Letters 25 (3), 135-137, 2004 | 200 | 2004 |
| Fabrication and mobility characteristics of ultra-thin strained Si directly on insulator (SSDOI) MOSFETs K Rim, K Chan, L Shi, D Boyd, J Ott, N Klymko, F Cardone, L Tai, ... IEEE International Electron Devices Meeting 2003, 3.1. 1-3.1. 4, 2003 | 200 | 2003 |
| Three dimensional integrated circuit SM Alam, IM Elfadel, KW Guarini, M Ieong, PN Kudva, DS Kung, MA Lavin, ... US Patent 7,312,487, 2007 | 192 | 2007 |
| CMOS circuit performance enhancement by surface orientation optimization L Chang, M Ieong, M Yang IEEE Transactions on Electron Devices 51 (10), 1621-1627, 2004 | 191 | 2004 |
| Modeling line edge roughness effects in sub 100 nanometer gate length devices P Oldiges, Q Lin, K Petrillo, M Sanchez, M Ieong, M Hargrove 2000 International Conference on Simulation Semiconductor Processes and …, 2000 | 191 | 2000 |
| High-performance CMOS devices on hybrid crystal oriented substrates BB Doris, KW Guarini, M Ieong, S Narasimha, K Rim, JW Sleight, M Yang US Patent 7,329,923, 2008 | 189 | 2008 |
| Hybrid-orientation technology (HOT): Opportunities and challenges M Yang, VWC Chan, KK Chan, L Shi, DM Fried, JH Stathis, AI Chou, ... IEEE Transactions on Electron Devices 53 (5), 965-978, 2006 | 187 | 2006 |
